The present invention relates generally to performing addition operations in an arithmetic logic unit (ALU) in a computing system and more particularly to sequential adding operations on one or more binary coded decimal (BCD) operands.
Most calculations performed in an ALU can be accomplished utilizing simple addition. Multiplication, for example, is a sequence of repeated addition operations on an operand. Decimal numbers or data are generally expressed in groups of four binary bits per digit (BCD). Since the four binary bits are capable of coding up to a hexadecimal digit, if used to code a decimal digit, the BCD digit has to be prebiased by adding an excess six to the digit prior to performing additional operations. At the completion of the additional operation the excess six previously added has to be subtracted out from all of the digits in which a carry did not result from the addition operation. If a calculation requires a sequence of repeated addition operations, the excess six has to be subtracted out from the resultant of the first operation and then has to be added in for the next addition operation, thus two intermediate operations are required between each addition operation in a sequence of repeated addition operations.